Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site oakhill.UUCP Path: utzoo!watmath!clyde!burl!ulysses!allegra!mit-eddie!godot!harvard!seismo!ut-sally!oakhill!cruess From: cruess@oakhill.UUCP (Michael Cruess) Newsgroups: net.micro.68k Subject: Re: bus error, but why? Message-ID: <311@oakhill.UUCP> Date: Fri, 1-Feb-85 10:04:27 EST Article-I.D.: oakhill.311 Posted: Fri Feb 1 10:04:27 1985 Date-Received: Sun, 3-Feb-85 08:45:23 EST References: <363@nbs-amrf.UUCP> Reply-To: cruess@oakhill.UUCP (Michael Cruess) Organization: Motorola Inc. Austin, Tx Lines: 20 Summary: In article <3500007@iuvax.UUCP> jec@iuvax.UUCP writes: > > Is there a performance different >on either the 68010 or 68020 with regards to alignment (long v. word)? > On the MC68000 and MC68010, there is no penalty for aligning a long word on a word boundary. It always takes 2 bus cycles to access a long. Words and longs may not be aligned on odd byte boundaries. On the MC68020, there are no alignment restrictions on data, but there may be a performance penalty depending on the alignment and data bus width. The MC68020 can handle memory that is 8, 16, and/or 32 bits wide. If an operand spans more than one addressable "unit" of memory the processor will automatically run the minimum number of cycles to complete the transfer. The number can range from 1 (long aligned long in 32 bit memory) to 4 (any long in 8 bit memory). The most interesting is 3 (odd byte aligned long in 16 bit memory). Michael Cruess {ihnp4,seismo,gatech,ctvax}!ut-sally!oakhill!cruess