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From: mwm@ucbtopaz.CC.Berkeley.ARPA
Newsgroups: net.micro.68k
Subject: Re: Why no INC or DEC
Message-ID: <669@ucbtopaz.CC.Berkeley.ARPA>
Date: Mon, 21-Jan-85 19:13:18 EST
Article-I.D.: ucbtopaz.669
Posted: Mon Jan 21 19:13:18 1985
Date-Received: Thu, 24-Jan-85 07:14:31 EST
References: <242@talcott.UUCP> <246@talcott.UUCP>
Reply-To: mwm@ucbtopaz.UUCP (Praiser of Bob)
Distribution: net
Organization: Univ. of Calif., Berkeley CA USA
Lines: 19
Summary: 

In article <246@talcott.UUCP> gjk@talcott.UUCP (Greg Kuperberg) writes:
>> Why doesn't the 68000 have increment or decrement instructions?
>
>And the answer is (thanx for all the replies) that you can use ADDQ and
>SUBQ, since those instructions only take up one word.  Nevertheless, I
>wince when I see "ADDQ #1,D0", even if it does have a Q in it.  I claim
>this is a natural tendency, since this kind of thing really is inefficient
>on other CPU's.  I advise making an INC and DEC macro if you also have this
>tendency.
>			Greg Kuperberg
>		     harvard!talcott!gjk
[Excuse me while I retch.]

Rather than having an INC & DEC macro, how about getting a smart assembler
that know that "ADD #n,D0" can be turned into an ADDQ instruction for
small n? That way, you get some measure of orthogonality in the source.
If you have a natural preference for such, I advise you to do so.

	<mike