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From: jerry@oliveb.UUCP (Jerry Aguirre)
Newsgroups: net.arch
Subject: Re: Cube designs vs. x,y,z bus
Message-ID: <268@oliveb.UUCP>
Date: Thu, 21-Feb-85 20:49:21 EST
Article-I.D.: oliveb.268
Posted: Thu Feb 21 20:49:21 1985
Date-Received: Sat, 23-Feb-85 00:41:34 EST
References: <48@pbear.UUCP>
Organization: Olivetti ATC, Cupertino, Ca
Lines: 42

Incorporating an x,y,z bus design may simplify the resulting
configuration but does place limits on the number of processors.  Also
a correction:  the data would have to pass thru at most 2 intermediate
processors to reach its destination.  Along 1 axis to the plane
containing the destination, then into the line containing the
destination, then to the destination.  One intermediate connection
would be required if the processors were in a plane (x, y only).  The
x,y,z bus would allow for 3 equal paths for any source and destination
so fault tolerance and even bus loading could be handled.

When you begin to expand the number of processors the limits of the
x,y,z design are obvious.  The originators of the hyper-cube are
talking about VERY large arrays of processors.  As I understand it, it
takes about 6 months of compute time on a Cray computer to create about
1 hour of visual images (like the graphics for the movie "The Last
Starfighter").  And even then the resolution is not as good as it could
be.  This is one kind of problem for which a very large array of
processors is suited.

At some point the number of processors on a x,y,z bus is going to
exceed its capacity.  The limit on the number of processors is inherent
in the design spec of the bus.  With the hyper-cube the number of
connections grows with the log-2 of the number of processors.  So 1,000
processors require 10 connections per processor and 1,000,000(1M)
require 20.  A x,y,z design for 1M processors would have 100 processors
sharing each bus.

If your thinking that 1M processors is unreasonable then think again.
Depending on the memory in each processor 1 to several processors could
be placed on a single chip.  As the only IO required is for the
hyper-channel connections the number of pin-outs is minimal.  As a 1M
array would, by definition, get volume pricing each chip might cost
only a dollar or so.

If each processor had 16K bytes of memory, a 1M array would result in a
computer with 16,000 Meg (16 gigabytes) of ram.  If the entire wafer of
silicon was used then the wasted area used for cutting the chips apart
could be eliminated.  It would be possible to get many processors on on
wafer with only 30 or so external connections required.

				Jerry Aguirre @ Olivetti ATC
{hplabs|fortune|idi|ihnp4|tolerant|allegra|tymix}!oliveb!jerry