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From: wall@fortune.UUCP (Jim Wall)
Newsgroups: net.arch
Subject: Re: Cube designs vs. x,y,z bus
Message-ID: <5056@fortune.UUCP>
Date: Wed, 27-Feb-85 11:51:30 EST
Article-I.D.: fortune.5056
Posted: Wed Feb 27 11:51:30 1985
Date-Received: Wed, 27-Feb-85 21:28:12 EST
References: <48@pbear.UUCP> <268@oliveb.UUCP> <7306@watrose.UUCP>
Reply-To: wall@fortune.UUCP (Jim wall)
Organization: Fortune Systems, Redwood City, CA
Lines: 31

>The x.y.z (or u.v.w.x.y.z) bus schema don't buy you anything. You get
>buckets of bus squabbling for each "plane" AND you must route data to a 
>different plane if the destination processor isn't connected to your plane.
>Point-to-point, on the other hand, buys zero bus squabbling (i.e. full bus
>bandwidth on each wire), at the price of data for "distant" processors
>having to be routed through some intermediaries.
>
>Chris Shaw

   Ah, surely you jest.  Given that each node on the psuedo cube has 
its own associated memory, the vast majority of that processors time
will be spent without touching the 'bus'.  And in most cases, the only
times the bus is used is for infrequent data movement (lets say for 
mmu misses) and for interprocessor communication.

   As long as there are not too many processors on any one bus or e
ethernet link, the number of times where you would have to wait for the
bus would be minimal. The trade off as to how many would be allowed
is part of the architects job, to analyze the usage of the machine, the
tasks it must do, the performance requirements and the cost. Outside of
accademia and government, cost is much more important than unnecessary
performance.

   These ideas are, of course, not new. Rob Warnocks (redwood!rpw3)
message on 'fat corners' imply the same thing. For some cases, a node
may have to communicate through a gateway node to get to the processor
it wishes to talk to. This approach is equivilent to more processors
on one plane, as far as the delay aspects are concerned.

						-Jim Wall
					     ...amd!fortune!wall