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From: zben@umd5.UUCP
Newsgroups: net.arch
Subject: Re: Cube designs vs. x,y,z bus
Message-ID: <344@umd5.UUCP>
Date: Mon, 25-Feb-85 03:23:03 EST
Article-I.D.: umd5.344
Posted: Mon Feb 25 03:23:03 1985
Date-Received: Thu, 28-Feb-85 01:16:12 EST
References: <48@pbear.UUCP> <268@oliveb.UUCP> <342@umd5.UUCP>
Reply-To: zben@umd5.UUCP (Ben Cranston)
Organization: U of Md, CSC, College Park, Md
Lines: 16
Summary: Oops, More 

In article <342@umd5.UUCP> zben@umd5.UUCP (Ben Cranston) writes:
>So you might have to burn a map of the good processors into the chip after
>testing, like those Intel mag bubble chips...  

Er, um, lets be charitable and say ZBEN wasn't really thinking when he 
said "Intel".  He must have been thinking of the "T.I." bubble chips...

And its even worse than that.  A bad processor area could short one of the
power supply rails, or (in the case of the Ethernet scheme) could flood the
Enternet with bogus messages.  The chip would probably have to have areas
where a bad processor (identified during testing) could be electrically
isolated from the power supply rails and the network connection, using a
directed-energy beam to vaporize strategic areas of metallization.

-- 
Ben Cranston        ...seismo!umcp-cs!cvl!umd5!zben    zben@umd2.ARPA