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From: jk@duke.UUCP (Judd Knott)
Newsgroups: net.arch,net.wanted
Subject: wanted: info on wafer-scale integration
Message-ID: <5492@duke.UUCP>
Date: Tue, 26-Feb-85 10:24:13 EST
Article-I.D.: duke.5492
Posted: Tue Feb 26 10:24:13 1985
Date-Received: Fri, 1-Mar-85 07:08:43 EST
Organization: Duke University
Lines: 26
Xref: watmath net.arch:873 net.wanted:5894

At a recent VLSI workshop there was some talk of an attempt at wafer-scale
integration at Trilogy.  I received this information second hand and I am
extremely interested in any information concerning this (or other) wafer-
scale projects.  In particular I am interested in the yield, the number, causes,
and distribution of defects, the technology and feature size of the project,
and what kind of (if any) fault-tolerant techniques were introduced to enhance
the yield.  The information about Trilogy's project was rather sketchy; all I
heard was that yield was 0%.  I know that data concerning process and yield is
not circulated indiscriminately, but I would be more than willing to sign 
non-disclosure agreements for anyone willing to enlighten me.  My research is
in fault-tolerant design methodologies for wafer-scale VLSI parallel processing
arrays.  My only knowledge of yield statistics is what is reported in the 
literature in the form of vague and unsubstantiated proclamations.  Your 
assistance will be greatly appreciated.

Thank You.

Judson D. Knott
Duke University
Department of Computer Science
Durham, NC 27707

(919) 684-5110  ext: 26

duke!jk