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From: jewett@hplabs.UUCP (Bob Jewett)
Newsgroups: net.rumor,net.chess,net.arch
Subject: Re: Ballistic transistors, the Belle II chess machine, & Seymour Cray
Message-ID: <1729@hplabs.UUCP>
Date: Thu, 14-Mar-85 12:46:15 EST
Article-I.D.: hplabs.1729
Posted: Thu Mar 14 12:46:15 1985
Date-Received: Fri, 15-Mar-85 04:07:54 EST
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Organization: Hewlett Packard Labs, Palo Alto CA
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Xref: watmath net.rumor:685 net.chess:813 net.arch:982

> >  Of course, the ballistic gate speeds (100 femtosecond range) combine with
> > a sub-picosecond cycle time and the speed of light to require a single-chip
> > implementation.
> >     -- James A. Woods   {research,ihnp4,hplabs}!ames!jaw  (or, jaw@riacs)

>                    For years, people have been trying to speed up the
> switching speed of logic circuits, and the very fastest to date is
> about 10 picoseconds delay per gate, achieved using the technology
> known variously as HEMT, SDHT, MODFET, and TEGFET, all of which are
> the exact same thing and which have been around for about five years
> or more.
> --J. Abeles     mhuxm!abeles

Nope.  Try Josephson junctions.  Gate delays less than 10ps have been
reported by the Japanese.  IBM reported 13ps delay in a string of OR
gates, 6ps of which was propagation down terminated superconducting
transmission lines.  The 13ps number translates into ~40ps gate delays
with reasonable margins and fan-in/fan-out.

Bob Jewett   hplabs!jewett