Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.2 9/18/84; site wateng.UUCP
Path: utzoo!watmath!wateng!ksbszabo
From: ksbszabo@wateng.UUCP (Kevin Szabo)
Newsgroups: net.lsi,wat.vlsi
Subject: I need a reference for the `Picket Fence Algorithm'
Message-ID: <2199@wateng.UUCP>
Date: Thu, 21-Mar-85 21:51:16 EST
Article-I.D.: wateng.2199
Posted: Thu Mar 21 21:51:16 1985
Date-Received: Fri, 22-Mar-85 02:56:41 EST
Distribution: net
Organization: VLSI Group, U of Waterloo
Lines: 18
Xref: watmath net.lsi:96 wat.vlsi:89

Some time ago I read a paper on a compaction algorithm.
The algorithm was known as `picket fence', and it was
utilitized in the compaction of virtual grid symbolic layouts.

Well, its time to write my dissertation and I can't find
the <expletive> thing. Has anybody out there heard of this
algorithm, and can they tell me what paper I read it in
(yes I know it sounds foolish).

I believe the paper was describing work at MCNC, possibly
part of the VIVID project (i.e. had some ABCD stuff thrown
in). Other keywords: mulga, virtual grid, compaction ...

Any pointers appreciated!

				Kevin
-- 
Kevin Szabo  watmath!wateng!ksbszabo (U of Waterloo VLSI Group, Waterloo Ont.)