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From: doug@terak.UUCP (Doug Pardee)
Newsgroups: net.micro.16k
Subject: Re: 32xxx bus cycles & CPU speed
Message-ID: <446@terak.UUCP>
Date: Fri, 15-Mar-85 12:13:08 EST
Article-I.D.: terak.446
Posted: Fri Mar 15 12:13:08 1985
Date-Received: Wed, 20-Mar-85 03:55:43 EST
References: <928@sjuvax.UUCP>
Organization: Terak Corporation, Scottsdale, AZ, USA
Lines: 29

> 1) The VAX memory access speed relies on write back cache - the bus cycles
> are 400 ns.  With a 10 Mhz 32032 *or* 32016 one can get real memory
> response times of 200ns.  This saves time.  

Say what????  200 ns bus cycle times on a 10 MHz 32K?  At 10 Mhz, each
clock is 100 ns.  Except for slave processor register accesses, the
shortest possible bus cycle on a 32xxx is 4 clocks.  That's 400 ns.
If you have an MMU, it's 5 clocks, or 500 ns.

One of the "unique" aspects of the 32xxx is that there's no point in
putting a memory cache on it, 'cause the bus cycle will take forever
anyway.

BTW, another "unique" aspect is that if you're using the TCU, there is
no usable specification for how rapidly the memory must respond on a
read operation.  The data must be ready 10 ns (CPU only) or 15 ns
(CPU w/MMU) before the falling edge of PHI2 in T3, but the TCU does
not have any timing specification for the falling edge of PHI2!

> 2) it is not clear that the 32016 doesn't compare to a VAX.  With the right 
> kind of paging algorithms and hardware, one might very well outperform an 
> 11/750 WITH FPA. I haven't tried it, but it looks possible.

My experience is that a 10 MHz 32016 w/MMU and FPU is in the same
ballpark as (or slightly faster than) a VAX 11/750.  But -- the C
compiler supplied with Genix is terribly slow, taking twice as long
as the VAX/UNIX C compiler.
-- 
Doug Pardee -- Terak Corp. -- !{hao,ihnp4,decvax}!noao!terak!doug