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From: agn@cmu-cs-k.ARPA (Andreas Nowatzyk)
Newsgroups: net.micro.68k
Subject: Min clock frequency for 68020
Message-ID: <318@cmu-cs-k.ARPA>
Date: Sun, 17-Mar-85 21:12:16 EST
Article-I.D.: cmu-cs-k.318
Posted: Sun Mar 17 21:12:16 1985
Date-Received: Tue, 19-Mar-85 06:07:51 EST
Organization: Carnegie-Mellon University, CS/RI
Lines: 13

According to our information, the min clock frequency for the
68020 is 8Mhz. Does anyone know if it is possible to clock it
reliably at a lower rate, say about 1Mhz? How about cooling the
chip (to reduce the leakage current)?

The reason for this question is that we would like to run it
in an simulated environment (Megalogician with PMX) to debug
the circuit and the simulator-adapter cannot handle 8 Mhz.
I'm also curious for the physical reason for this rather
high lower bound.

   Thanks  --  Andreas     Usenet:  ...!seismo!cmu-cs-k!agn
                           Arpa:   Andreas.Nowatzyk@cmu-cs-k.arpa