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From: david@daisy.UUCP (David Schachter)
Newsgroups: net.micro,net.micro.pc
Subject: Re: Standard, What standard???
Message-ID: <87@daisy.UUCP>
Date: Sun, 10-Mar-85 01:11:16 EST
Article-I.D.: daisy.87
Posted: Sun Mar 10 01:11:16 1985
Date-Received: Wed, 20-Mar-85 04:59:11 EST
References: <143@idmi-cc.UUCP> <810@sjuvax.UUCP> <56@daisy.UUCP> <287@cmu-cs-k.ARPA> <77@daisy.UUCP> <1068@watdcsu.UUCP>
Reply-To: david@daisy.UUCP (David Schachter)
Organization: Daisy Systems Corp., Mountain View, Ca
Lines: 63
Xref: watmath net.micro:9756 net.micro.pc:3522

In article <1068@watdcsu.UUCP>, Rick Sellens writes:
>In article <77@daisy.UUCP> david@daisy.UUCP (David Schachter) writes:
>>
>>In our experience writing CAE software, in the rare cases where 64K segment
>>ation is a problem, it usually means that we don't know what we are doing yet.
>>There is almost always a better algorithm that we haven't discovered yet, one
>> which uses smaller data structures >faster<.
>>
>>Large address spaces are convenient.  They are not essential.  Moreover, their
>>convenience can rob you of the incentive to get maximum performance.  The
>>Intel architecture is a dark cloud with a silver lining: the need to keep 
>>within the small address space frequently causes us to find solutions that are
>>smaller and faster, helping us meet our performance goals.
>
>
>I understand this to mean that it is desirable to have arbitrary restrictions
>imposed on your software development by a hardware design. (By arbitrary I
>mean that the restriction, in this case 64K addressable by 16 bits, has
>nothing to do with the application, but is dictated by the hardware.)
... (omitted text) ...
>
>I hate to hear restrictive hardware designs defended as "good in themselves".
>Hardware restrictions will always be with us, but they are never desirable.

Bosh and twaddle, Mr. Sellens.  Normally, I would assume that my posting was
unclear.  In this case, I believe it was clear and you mis-interpreted it.
Small address spaces are not good, in and of themselves.  But they force you
to find smaller algorithms which often run faster as well.  I don't know why
smaller algorithms >tend< to run faster; I'm not a philosopher.

In the applications I write, CAE programming, the small address space of the
miserable Intel architecture does not often cause pains.  When it does, it
is usually because the algorithm stinks.  The effort to find an algorithm
which uses less space often produces, as a nice side effect, a program that
runs faster.

Mr. Sellens claims that 'fast enough' is often sufficient and he would be
correct if he was talking about a single-job CPU.  But in the real world,
systems frequently run multiple jobs.  Any spare cycles left over by a pro-
gram that runs 'too fast' are available for other programs.

The Intel architecture provides the ability to write very fast programs.  It
provides the ability to write very small programs.  If you want to provide the
best price-performance ratio for your customers, the Intel architecture can be
a good choice.  If your only goal is to get something out the door, other
architectures are better.

Mr. Sellens also states that with the coming availability of 32 bit micro-
processors, the speed advantage of a processor that uses 16 bits as the
native object size will disappear.  (The argument is that if you have a
16 bit bus, you don't want to deal with 32 bit quantities when 16 bits will
do.)  Mr. Sellens is right.  SOME DAY, 32 bit machines will be available
in production quantity.  But they are not available now.  Our customers
don't want to wait a year or two.  They want solutions now.

Architectural chavinism helps no one.  I don't like the Intel architecture.
But it is not the swamp that others make it out to be.

[The opinions expressed above are my own and not necessarily those of Daisy
Systems Corporation, its employees, or subsidiaries.  If anyone else would
like these opinions, they are available for $40 each, $75 for two.]
{Eight foot four, mouth that roars, pitch storm troopers out the door, has
anybody seen my Wookie?}