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Path: utzoo!linus!philabs!cmcl2!acf4!tsc2597
From: tsc2597@acf4.UUCP (Sam Chin)
Newsgroups: net.micro.cpm
Subject: Re: Dynamic Memory
Message-ID: <1010008@acf4.UUCP>
Date: Fri, 15-Mar-85 21:24:00 EST
Article-I.D.: acf4.1010008
Posted: Fri Mar 15 21:24:00 1985
Date-Received: Sun, 17-Mar-85 22:05:24 EST
References: <8809@brl-tgr.ARPA>
Organization: New York University
Lines: 42

<<<>>>

From my (minimal) knowledge about chip design, I seem to recall that for
a given technology (say NMOS), a single bit of a static ram consisted of
a master slave flip flop which retains its value once set. On the other hand
a bit from a dynamic ram could be made quite simply from two transistors and
two inverters in the form:

                |
               ___
               ___
              |   |          |    = transistor
           ___|   |______   ---  
           |            |
      |    |            o    >o   = inverter
     ___   |            ^
     ----------->o------|

and that the above could be refreshed by a 2 phase clock since the charge
eventually leaks. From this I can conclude that dynamic rams can be made
denser and faster than static rams (master slave flip flops require much
more logic per bit). Since the charge does not leak that often (say once
a minute or so in room temperature) and that they use so much less logic,
they should also consume less power than static rams. Also the above dynamic
ram design is suitable for implementation in VLSI.

Why then is a 256K static ram board $1500 and 256K of dynamic ram chips
merely $100? Why can I get static ram which will run with a 12 Mhz 68000,
a 8 Mhz 80286 and a 8Mhz Z80 and not dynamic ram which will do the same?
Why does every one advertise static ram as "low power". Am I looking at
different technologies (NMOS vs CMOS)? What is the S-100 standard for 
providing a signal to the ram board for dynamic ram refresh? If there is
why doesn't everyone adhere to it? I also believe that a dynamic ram 
controller such as the Intel 8203 has an internal timer which will provide
fail safe refresh. Other than that to minimize wait states due to refresh
cycles, one could generate a refresh request whenever a bus cycle occurs
and memory is not accessed (for example during an I/O cycle)


                                           Sam Chin
                                           allegra!cmcl2!acf4!tsc2597
                                           tsc2597.acf4@nyu