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Path: utzoo!watmath!watcgl!jchapman
From: jchapman@watcgl.UUCP (john chapman)
Newsgroups: net.micro.cpm
Subject: Re: Dynamic Memory
Message-ID: <1488@watcgl.UUCP>
Date: Mon, 18-Mar-85 09:46:21 EST
Article-I.D.: watcgl.1488
Posted: Mon Mar 18 09:46:21 1985
Date-Received: Tue, 19-Mar-85 03:37:50 EST
References: <8809@brl-tgr.ARPA> <1010008@acf4.UUCP>
Organization: U of Waterloo, Ontario
Lines: 63

> Why then is a 256K static ram board $1500 and 256K of dynamic ram chips
> merely $100? Why can I get static ram which will run with a 12 Mhz 68000,
> a 8 Mhz 80286 and a 8Mhz Z80 and not dynamic ram which will do the same?
> Why does every one advertise static ram as "low power". Am I looking at
> different technologies (NMOS vs CMOS)? What is the S-100 standard for 
> providing a signal to the ram board for dynamic ram refresh? If there is
> why doesn't everyone adhere to it? I also believe that a dynamic ram 
> controller such as the Intel 8203 has an internal timer which will provide
> fail safe refresh. Other than that to minimize wait states due to refresh
> cycles, one could generate a refresh request whenever a bus cycle occurs
> and memory is not accessed (for example during an I/O cycle)
> 
> 
>                                            Sam Chin
>                                            allegra!cmcl2!acf4!tsc2597
>                                            tsc2597.acf4@nyu
 
 1. current prices are more like $1000 for 256k static boards and
    $600 for 256k dynamic (not quite as big a price difference as
    you have indicated.
 
 2. drams are generally denser (x4) than statics.
 
 3. dynamic ram chips are themselves much cheaper than static, probably
    due in part to the fact that mainframe manufacturers use zillions
    of them and therefore spread (chip) costs over a larger base.
 
 4. there is no s100 standard for a refresh signal, this is precisely
    the problem
 
 5. why does static always work? because all it does is read/write
    cycles -> simpler board design, timing requirements etc.  On the
    other hand dynamic has to make sure it gets (64/128/256) refresh
    cycles every 1 or 2 ms.  The bus standard makes no allowance for
    this so the memory board has to squeeze them in whenever it
    thinks it is safe.  The failsafe refresh you refer to is from
    the ram chips point of view - the 8203 will always keep it
    refreshed - not from the bus masters point of view ( to take
    things to an absurd point: you could have the ram controller
    devote 100% of cycles to refresh, which would be failsafe but
    is not something you are likely to be happy with).
 
 6. Using i/o cycles to do hidden refresh will not help much (how
    much of the bus time is spent doing this).  The big problem
    is that you have to come up with a scheme that guarantees
    adequate refreshing 100% of the time (99.99999% is not good
    enough).  The bus standard is precisely that - it places
    certain requirements on the signals on the bus and not really
    on the cpu - e.g. all refreshing eventually depends on being
    able to stall the current bus master to do a refresh cycle;
    an 8086 wants the ready signal/status during T2, if you design
    a board to accomodate this will it also fulfill the requirements
    of a dma disk controller? or a Z80? or a 68000? or a Z8000?
    or a 32016? or a 6800? (Gods reputed action at the tower of babel
    was viewed as a curse for good reason :-).

 7. If you could guarantee strict adherence to the timing in
    IEEE/696 of all the cpu boards and dma boards that you want
    to use then it should certainly be possible to contruct a
    dynamic board for the s100 that would work in all situations
    but it by no means a trivial task.
 
    John