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Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxt!houxm!hou2d!afb3
From: afb3@hou2d.UUCP (A.BALDWIN)
Newsgroups: net.lang.c,net.arch
Subject: Re: Time penalty for non-alignment on VAX/780
Message-ID: <525@hou2d.UUCP>
Date: Mon, 1-Apr-85 17:20:58 EST
Article-I.D.: hou2d.525
Posted: Mon Apr  1 17:20:58 1985
Date-Received: Tue, 2-Apr-85 07:24:12 EST
References: <9251@brl-tgr.ARPA> <317@cmu-cs-k.ARPA> <9277@brl-tgr.ARPA> <330@calgary.UUCP>, <434@unisoft.UUCP>
Organization: AT&T Bell Labs, Holmdel NJ
Lines: 29
Xref: watmath net.lang.c:4902 net.arch:1064

NO-NO-NO!!!!

The SBI is not 64-bits wide.  SBI transactions occur as follows:

	Address (30 bits on 32 bit bus)
	data	(32-bits on 32 bit bus)
	data	(32-bits on 32 bit bus)

All other transactions are "special" (and slow things down!@#$%^&).
The 11/780 has memory organized in 64-bit chunks which can cause
real problems on memory writes (the memory systems has to read the
data, mask in the new stuff, then write the data... sorta like core,
remember??).  If you read the info on the UBA's and MBA's the SBI
interaction is described in detail (hardware handbook).

The cache is two-way set associative (ie. as you say it reads 64-bits
on a miss) write-through cache.  The write through feature really 
slows things on non-aligned transfers for the reason above.  Also, it 
is unclear from the documentation (VAX hardware handbook) that the 
cache organization is quad-word oriented.  In fact most of the VAX cpu 
functions are byte oriented and I would suspect that cache to be also.


Al Baldwin
AT&T-Bell Labs
...!ihnp4!hou2d!afb3


[These opinions are my own....Who else would want them!!!]