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From: brooks@lll-crg.ARPA (Eugene D. Brooks III)
Newsgroups: net.micro,net.micro.68k,net.micro.16k
Subject: Re: Re: Floating Point Comparisons
Message-ID: <494@lll-crg.ARPA>
Date: Fri, 5-Apr-85 01:19:55 EST
Article-I.D.: lll-crg.494
Posted: Fri Apr  5 01:19:55 1985
Date-Received: Sun, 7-Apr-85 03:20:53 EST
References: <133@cfa.UUCP> <6370@boring.UUCP>
Distribution: net
Organization: Lawrence Livermore Labs, CRG group
Lines: 25
Xref: watmath net.micro:9948 net.micro.68k:709 net.micro.16k:313

> 
> In article <133@cfa.UUCP> ward@cfa.UUCP (Steve Ward) writes:
> >       Computer
> >          or
> >     Microprocessor           FADD  FSUB  FMUL  FDIV  DADD  DSUB  DMUL  DDIV
> >=========================     ====  ====  ====  ====  ====  ====  ====  ====
> >	...
> >NS32016/NS32081 10 MHZ        7.40  7.40  4.80  8.90  7.40  7.40  6.20 11.90
> >
> >NS32016/NS32081 8 MHZ         9.25  9.25  6.00 11.13  9.25  9.25  7.75 14.86
> >
> Is this true? It *does* sound funny to me that additions and
> subtractions take longer than multiplies....
> The only thing I can imagine from the table is that *ADD/*SUB are always
> done in double mode, but this doesn't seem to make sense if there is
> hardware to do multiplies/divides in single precsision.
> 
> Can anyone enlighten me on this???
Yes its true that an fadd takes longer than a fmult on the NS32032 according
to the NS manual.  I assume that NS knows what the timing is for their HW.

A floating point add or subtract requires a shift if the mantessa to get
the exponents to agree before adding.  The multiply does not require this.
Perhaps the 16081 has to do the shift a bit at a time in microcode.
Anyone from National on the net to answer this one?