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From: jack@boring.UUCP
Newsgroups: net.micro,net.micro.68k,net.micro.16k
Subject: Re: Floating Point Comparisons
Message-ID: <6370@boring.UUCP>
Date: Wed, 3-Apr-85 11:25:54 EST
Article-I.D.: boring.6370
Posted: Wed Apr  3 11:25:54 1985
Date-Received: Sun, 7-Apr-85 06:46:57 EST
References: <133@cfa.UUCP>
Reply-To: jack@boring.UUCP (Jack Jansen)
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In article <133@cfa.UUCP> ward@cfa.UUCP (Steve Ward) writes:
>       Computer
>          or
>     Microprocessor           FADD  FSUB  FMUL  FDIV  DADD  DSUB  DMUL  DDIV
>=========================     ====  ====  ====  ====  ====  ====  ====  ====
>	...
>NS32016/NS32081 10 MHZ        7.40  7.40  4.80  8.90  7.40  7.40  6.20 11.90
>
>NS32016/NS32081 8 MHZ         9.25  9.25  6.00 11.13  9.25  9.25  7.75 14.86
>
Is this true? It *does* sound funny to me that additions and
subtractions take longer than multiplies....
The only thing I can imagine from the table is that *ADD/*SUB are always
done in double mode, but this doesn't seem to make sense if there is
hardware to do multiplies/divides in single precsision.

Can anyone enlighten me on this???
>Weitek WTL1164,WTL1165         -     -   0.360   -     -     -   0.600   -
>
>The Weitek line is very bare.  The fact that an MC68020 floating point
>coprocessor is being manufactured by Weitek is interesting, and it at least
>promises to be very fast.  Perhaps someone else can look into the Weitek
>situation.  The trade journal "new product" information was pretty flaky.
>
>
>Steven M. Ward
>Center for Astrophysics
>60 Garden Street
>Cambridge, MA 02138
>(617) 495-7466
>{genrad, allegra, ihnp4, harvard}!wjh12!cfa!ward


-- 
	Jack Jansen, {decvax|philabs|seismo}!mcvax!jack
It's wrong to wish on space hardware.