Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.2 9/18/84; site spar.UUCP
Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxt!houxm!whuxl!whuxlm!harpo!decvax!decwrl!spar!baba
From: baba@spar.UUCP (Baba ROM DOS)
Newsgroups: net.micro
Subject: Re: ANOTHER 32-BIT MACHINE???
Message-ID: <150@spar.UUCP>
Date: Sun, 31-Mar-85 17:24:06 EST
Article-I.D.: spar.150
Posted: Sun Mar 31 17:24:06 1985
Date-Received: Tue, 2-Apr-85 06:56:40 EST
References: <9254@brl-tgr.ARPA>, <1549@watcgl.UUCP> <5355@utzoo.UUCP> <5371@utzoo.UUCP>
Organization: Schlumberger Palo Alto Research, CA
Lines: 30

> My statement was indeed that binary compatibility with an 8086 is
> fundamentally incompatible with a full 32-bit architecture.  The 8086
> is not a 32-bit architecture, and does not extend gracefully into one.
> An 8086-compatible machine and a full 32-bit architecture are two
> different cpus; whether they happen to be on the same silicon, with a
> mode bit switching between them, is quite irrelevant to how useful
> the combination is.  Use of 8086 compatibility and use of full 32-bit
> architecture cannot occur simultaneously, even though Intel is trying
> to fake you out into believing they can.

Technical information and even a few advance data sheets for the 386 have
circulating for over a year now.  Henry obviously needs no such data in
order to pontificate on its architecture.  Some of the rest of you may
be interested in what I've been able to find out.  The 386 has essentially 
the same (pathetic) register architecture as the 8086, except that each
register is 32 bits long.  In 8086 mode or 286 mode, it will only use
the bottom 16 bits of each.  The ALU is presumably also partitioned into 
two 16 bit slices.  The tightly coupled CPU/MMU can change mode on the fly
on the basis of information in the segment descriptor for the code segment.

In 386 mode, each segment is to provide a linear 32-bit address space,
as opposed to the ghastly 64k segments of the 8086 and 286.

It is really not all that difficult to build a multi-mode CPU, but it
does tend to add a lot of circuitry in areas that you'd prefer to keep 
clean, and the added complexity increases the probability of design error,
without contributing anything to the native-mode performance.  It remains
to be seen just what performance Intel can deliver, and when.

					Baba ROM DOS