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From: srm@nsc.UUCP (Richard Mateosian)
Newsgroups: net.micro,net.micro.68k,net.micro.16k
Subject: Re: Floating Point Comparisons
Message-ID: <2574@nsc.UUCP>
Date: Sun, 7-Apr-85 04:42:41 EST
Article-I.D.: nsc.2574
Posted: Sun Apr  7 04:42:41 1985
Date-Received: Mon, 8-Apr-85 02:00:26 EST
References: <133@cfa.UUCP> <6370@boring.UUCP>
Reply-To: srm@nsc.UUCP (Richard Mateosian)
Distribution: net
Organization: National Semiconductor, Sunnyvale
Lines: 19
Xref: watmath net.micro:9966 net.micro.68k:712 net.micro.16k:316
Summary: 

In article <6370@boring.UUCP> jack@boring.UUCP (Jack Jansen) writes:

>>     Microprocessor           FADD  FSUB  FMUL  FDIV  DADD  DSUB  DMUL  DDIV
>>=========================     ====  ====  ====  ====  ====  ====  ====  ====
>>NS32016/NS32081 10 MHZ        7.40  7.40  4.80  8.90  7.40  7.40  6.20 11.90

>Is this true? It *does* sound funny to me that additions and
>subtractions take longer than multiplies....

It's true that adds take longer than multiplies on the NS32081.  It's because
adds are done by repeated multiplications ( :-) ).

The real reason is that there is fancier multiplication hardware on chip than
addition hardware.  Besides, additions require a normalization step before
the operation as well as after.

-- 
Richard Mateosian
{allegra,cbosgd,decwrl,hplabs,ihnp4,seismo}!nsc!srm    nsc!srm@decwrl.ARPA