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From: BillW@SU-SCORE.ARPA (William Chops Westfield)
Newsgroups: net.micro
Subject: Re: Floating Point Comparisons
Message-ID: <9904@brl-tgr.ARPA>
Date: Thu, 11-Apr-85 21:29:45 EST
Article-I.D.: brl-tgr.9904
Posted: Thu Apr 11 21:29:45 1985
Date-Received: Sun, 14-Apr-85 03:11:24 EST
Sender: news@brl-tgr.ARPA
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You are probably asking for too much.  Most of the floating point
chips available use the IEEE floating point format, which means
(I think) that they do all the math with 80 bit operands, and then
convert to 32 or 64 bit formats on input and/or output.

In the multply algorithm, you only have to calculate the most significant
24 bits of the product, right?  This may add to performance of the multiply.

Something I've always wondered about is whether any of the chips do
an N*N bit multiply in hardware, and then use less iterations to
get the final product - a 4*4 bit (unclocked) multiplier is not
very complicated - how much would it speed up a 64*64 bit multiply?
(Im too lazy to try to figure it out...)

BillW