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From: doug@terak.UUCP (Doug Pardee)
Newsgroups: net.micro
Subject: Re: AT&T's WE32100 Microprocessor
Message-ID: <526@terak.UUCP>
Date: Fri, 3-May-85 14:01:19 EDT
Article-I.D.: terak.526
Posted: Fri May  3 14:01:19 1985
Date-Received: Mon, 6-May-85 01:40:09 EDT
References: <714@houxl.UUCP>
Organization: Terak Corporation, Scottsdale, AZ, USA
Lines: 22

I must be getting ever more cynical in my old age.  I read the WE32100
info posted here, and my immediate reaction was that it must not be
a very impressive CPU.

This impression was brought about because they're touting the
fabrication technology (1.5 micron CMOS) and packaging (ceramic pin grid
arrays on 100 mil centers with gaps for routing channels), but haven't
said "boo" about the internal architecture, instruction set, and speed
(except for the FPU's speed).

Does it have registers?  How long does a memory cycle take?  What kind
of addressing modes are available?  Does it have any on-chip cache?  How
much time penalty does branching incur? Does it have separate I/O
addressing a la Intel, or is I/O memory mapped?  Can instructions
operate on 8, 16, and 32-bit data?  Do the operands have to be aligned
in memory?  Can it do a 32-bit multiply and divide?  Does it have string
handling instructions?  Does it have bit field instructions?

Was I supposed to have fallen to my knees and bowed my face to the
ground because this 32-bit processor announcement came from AT&T?
-- 
Doug Pardee -- Terak Corp. -- !{ihnp4,seismo,decvax}!noao!terak!doug