Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.2 9/18/84; site watmath.UUCP
Path: utzoo!watmath!atbowler
From: atbowler@watmath.UUCP (Alan T. Bowler [SDG])
Newsgroups: net.arch
Subject: Re: Re: I don't believe your statements abou
Message-ID: <14501@watmath.UUCP>
Date: Fri, 17-May-85 11:11:40 EDT
Article-I.D.: watmath.14501
Posted: Fri May 17 11:11:40 1985
Date-Received: Sat, 18-May-85 01:05:13 EDT
References: <7202@Glacier.UUCP> <36900002@ima.UUCP> <579@lll-crg.ARPA> <5593@utzoo.UUCP>
Reply-To: atbowler@watmath.UUCP (Alan T. Bowler [SDG])
Organization: U of Waterloo, Ontario
Lines: 11
Summary: 

In article <5593@utzoo.UUCP> henry@utzoo.UUCP (Henry Spencer) writes:
>The 67 had an unusual i/o architecture that tended to direct
>interrupts to the processor (if any) that wasn't busy at the time, which
>helped.

Actually I would not consider this at all unsual. Honeywell systems
back to the old GE 635 have done this.  Not all the software has
taken advantage of the capability, but the architecture supported it.
My general impression is that it is only IBM that has had conceptual
fixations about having a "master" cpu in multiprocessing configurations.
The lessons from the /67 were largely ignored for a long time.