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From: doug@terak.UUCP (Doug Pardee)
Newsgroups: net.micro.68k
Subject: Re: EA orthogonality
Message-ID: <550@terak.UUCP>
Date: Tue, 14-May-85 13:06:18 EDT
Article-I.D.: terak.550
Posted: Tue May 14 13:06:18 1985
Date-Received: Thu, 16-May-85 21:38:39 EDT
References: <419@oakhill.UUCP>
Organization: Terak Corporation, Scottsdale, AZ, USA
Lines: 54

> ... looking at over 7,000 instructions generated by
> Pascal and C compilers on the NS32032 we have found very little use
> of any memory to memory operations not already available on the M68000
> family. In fact, the National code (with half the registers of the M68000)
> only uses them about 2 percent of the time.

Jeepers, is the architecture of the 68xxx series being dictated entirely
by what instructions compilers use?  Why should a compiler care if the
instruction set is orthogonal or not?  The people who care are the
assembly language programmers.

Okay, what are the criteria we need to consider?

 1) Ease of programming in assembler -- the more flexible, the better.
 2) Size of object code -- it depends on whether the instruction words
    for the old register-type operations expand.  If not, then the
    memory-to-memory mode could only shrink the object code.
 3) Speed of execution -- this is a more complex issue.  Details follow.

The big advantage to having memory-to-memory instructions is that the
address of the destination is only computed once even though the
destination is also an operand.  If the address is quite complex this
means that a 4-instruction sequence (LEA,MOVE,operation,MOVE) can be
compressed into one instruction.  It also bypasses using two registers
(one for the address, one for the computation).

When we're considering speed of execution, we are almost totally
concerned with instructions which are located inside of loops.  Inside
of a loop, it might well be that the operations are done on values in
registers, with the operands loaded prior to entering the loop and
stored after exiting the loop.  In which case the memory-to-memory
instructions wouldn't be helpful.

If the performance of the CPU on the old register-type operations is
degraded by checking for memory-to-memory operations, then there would
be serious doubt about their value.  The NS32016 requires 4 clock cycles
to figure out that it's doing a register-to-register operation for most
instructions (the really important ones like MOV and ADD have been
suboptimized to remove that overhead).

A less obvious degradation occurs if the co-processors also support the
memory-to-memory operations.  The NS32081 FPU is a "slave" processor,
not a co-processor like the MC68881.  The difference is that when the
main CPU requests a floating-point operation, the National CPU has to
stop and wait for the operation to be done, because the result might
have to be stored back into memory.  The Motorola CPU does not have to
wait until it needs the FPU again, because the result will simply be
left in an FPU register.  (At least, that's the way I understand it).

In summary, memory-to-memory is fine, but I wouldn't tolerate very much
in the way of penalties to have it.
-- 
Doug Pardee -- Terak Corp. -- !{ihnp4,seismo,decvax}!noao!terak!doug
               ^^^^^--- soon to be CalComp