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From: heiss@spp2.UUCP (Robert Heiss)
Newsgroups: net.works
Subject: Re: PDP-8 Story
Message-ID: <590@spp2.UUCP>
Date: Mon, 13-May-85 16:07:34 EDT
Article-I.D.: spp2.590
Posted: Mon May 13 16:07:34 1985
Date-Received: Thu, 16-May-85 20:19:18 EDT
References: <1864@topaz.UUCP> <3500002@pbear.UUCP>
Reply-To: heiss@spp2.UUCP (Robert Heiss)
Organization: TRW, Redondo Beach  CA
Lines: 46

In article <3500002@pbear.UUCP> peterb@pbear.UUCP writes:
>
>What I would like to see is a proposal of a "next generation" PDP-8,
>
>Something with say:
>
>	16 bit memory
>	65K fields
>	256 fields (yields 24Mb memory)
>	each field broken to 256 256 word pages
>	direct addressing mode (so arryas and stuff don't have to be paged)
>	built in extended AU
>	other goodies.

Look at the 65816 microprocessor.  Except for the relative addressing on
short branches, its architecture is similar to your description.

>	Oh Yeah, a stack would be quite useful.

But not a *paged* stack.  If your hardware can only support a 256 byte
stack, why bother?  To support high-level language, you could emulate a
real stack by using indirect addressing (ala PDP-8, NOVA, APPLE ][).

>This type of architecture would encourage (NOT force) the programmer to
>write localized code for his routines. Also language compilers would be
>designed to take advantage of this concept.
>
>Also VM overhead would be smaller since the locality of page operations
>would keep paging activity lower than say a VAX. In fact I would not
>be suprised if this type of architecture could beat a VAX in terms of
>
>	(probably fit in less memory and run faster :-)
>
>Peter Barada

I'm intrigued by the VM overhead argument -- a paged-address-space CPU
connected to virtual memory with the same fixed page size -- has this
experiment been performed?

Coming soon:  Paged RISC + VM
	      vs.
	      MicroVAX II

Any volunteers to write a paged-memory C compiler?  :-)

	-Robert		!ihnp4!trwrb!trwspp!spp2!heiss