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From: rdt@houxk.UUCP (R.TRAUBEN)
Newsgroups: net.works
Subject: what is motorola mos vlsi 68851 mmu translation time?
Message-ID: <428@houxk.UUCP>
Date: Sun, 12-May-85 12:15:20 EDT
Article-I.D.: houxk.428
Posted: Sun May 12 12:15:20 1985
Date-Received: Tue, 14-May-85 08:20:55 EDT
Organization: ATT Information Systems, Holmdel, N.J.
Lines: 28

Hello:

Motorola claims 45 nanoseconds for 68851 translation time on the new
paged mmu (mos vlsi version. NOT either the ttl mini-board gate 
array version or its' unsuccessful parent, the 68451).

Does anyone know how they are defining the translation time parameter?
Measured from what event (as a starting reference) to what event
(as an ending point)? 

Virtual address 	valid to Physical address 	 valid?
Virtual address Strobe  valid to Physical address 	 valid? 
Virtual address Strobe  valid to Physical address STROBE valid? 
Does the Translation end point include the time to do access rights checking?
Will the MMU be constrained to run off the same clock as the CPU
to achieve this fast access time?

Any help is appreciated. I'm confused on what 45ns really means.

Thanks,

	> Richard

P.S. 	Address out times alone on 68xxx (*MOS) parts are in the vicinity
	of 30 nanoseconds!