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From: davet@oakhill.UUCP (Dave Trissel)
Newsgroups: net.works,net.micro.68k
Subject: Re: what is motorola mos vlsi 68851 mmu translation time?
Message-ID: <418@oakhill.UUCP>
Date: Mon, 13-May-85 16:31:32 EDT
Article-I.D.: oakhill.418
Posted: Mon May 13 16:31:32 1985
Date-Received: Thu, 16-May-85 02:29:00 EDT
References: <houxk.428>
Reply-To: davet@oakhill.UUCP (Dave Trissel)
Organization: Motorola Inc. Austin, Tx
Lines: 21
Xref: linus net.works:789 net.micro.68k:697

In article <428@houxk.UUCP> rdt@houxk.UUCP (R.TRAUBEN) writes:
>Hello:
>
>Motorola claims 45 nanoseconds for 68851 translation time on the new
>paged mmu (mos vlsi version. NOT either the ttl mini-board gate 
>array version or its' unsuccessful parent, the 68451).
>
>Any help is appreciated. I'm confused on what 45ns really means.
>

Sorry, but unless you have a non-disclosure agreement that information
should not be given to you.  (If you do then you should already have such
information.) You can contact your local Motorola sales office to arrange
for signing a non-disclosure agreement.

I can say that both the gate-array and the MC68851 versions support 1 cycle
translations and 0 cycle translations are possible for very fast logical
caches.

Motorola Semiconductor Inc.            Dave Trissel
Austin, Texas                 {ihnp4,seismo,gatech}!ut-sally!oakhill!davet