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From: kds@intelca.UUCP (Ken Shoemaker)
Newsgroups: net.micro.68k,net.arch
Subject: Re: Re: FLAME!!! Re: EA orthogonality
Message-ID: <584@intelca.UUCP>
Date: Thu, 23-May-85 15:17:40 EDT
Article-I.D.: intelca.584
Posted: Thu May 23 15:17:40 1985
Date-Received: Sat, 25-May-85 06:34:43 EDT
References: <419@oakhill.UUCP> <6415@boring.UUCP> <557@terak.UUCP> <6417@boring.UUCP>
Organization: Intel, Santa Clara, Ca.
Lines: 38
Xref: watmath net.micro.68k:796 net.arch:1244

> 
> [ Note that I added net.arch to the newsgroup, since this is probably
> where this discussion belongs]
> 
> >
> >The purpose of a CPU is *NOT* to be as easy to write a compiler for as
> >possible.
> Not agreed. If a machine is simple, the compiler is simpler, and thus it
> is available sooner, doesn't have as much bugs, etc.
> 
> This is also the whole point behind RISC architecture, one of the
> rising stars at the moment.
> -- 
> 	Jack Jansen, jack@mcvax.UUCP
> 	The shell is my oyster.

Not entirely true.

- the only instructions that can access memory are mov (or load) operations

- jumps jump only after the instruction after the jump has been executed

- some don't have hardware interlocks to prevent a register being read
  before a previous register write has completed, so you have to remember
  to do enough in between so you don't have problems.

- they don't allow arbitrary byte boundaries for code/data

You can argue that this is merely code reorganization, but they are
implemented this way such that you can eliminate both hardware pipeline
stages, and the delays in each stage that is there.  Just my impressions...
-- 
It looks so easy, but looks sometimes deceive...

Ken Shoemaker, Intel, Santa Clara, Ca.
{pur-ee,hplabs,amd,scgvaxd,dual,omovax}!intelca!kds
	
---the above views are personal.  They may not represent those of Intel.