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From: doug@terak.UUCP (Doug Pardee)
Newsgroups: net.micro.68k,net.arch
Subject: Re: RISC
Message-ID: <576@terak.UUCP>
Date: Tue, 28-May-85 13:30:41 EDT
Article-I.D.: terak.576
Posted: Tue May 28 13:30:41 1985
Date-Received: Fri, 31-May-85 02:41:16 EDT
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Organization: Terak Corporation, Scottsdale, AZ, USA
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Xref: linus net.micro.68k:770 net.arch:1084

> If we created the chip
> using only the instructions the compiler needed, we could use less logic.
> We could decode the instructions faster because the microcode is simpler
> (more ooomph per MHz), production is simpler, yield is higher, speeds are
> faster, and everyone is happy except the assembler programmer.
> ...
> This is the concept behind the RISC architecture ...

RISC is an interesting concept, but I have a major reservation.  Perhaps
someone can explain to me how on earth you're going to feed instructions
to a RISC machine fast enough?

All of the popular 8 and 16 bit microprocessors are speed limited by
instruction fetch, not by instruction complexity.  I will entertain the
objection that the 6502, with its critical shortage of on-chip
registers, is also limited by operand accesses.  The usual RISC machine
has lots of registers, so operand accesses shouldn't be a problem.
And nobody says that a non-RISC cpu can't have lots of registers.

The knee-jerk answer is "cache".  But that's only an answer if one
refuses to allow non-RISC cpus to use cache; they can fit more logic
into any given cache than can RISC cpus, thereby having a better "hit
ratio" than RISC.

Of course, one could design a RISC machine with a super-high-speed ROM
or cache in which one could store the commonly used functions like
multiplication and division, and then one would only have to fetch a
subroutine call from the (slow) instruction stream.

But doesn't that sound like your everyday, garden variety microcoded
non-RISC cpu?
-- 
Doug Pardee -- Terak Corp. -- !{ihnp4,seismo,decvax}!noao!terak!doug
               ^^^^^--- soon to be CalComp