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From: thoth@tellab3.UUCP (Marcus Hall)
Newsgroups: net.micro.68k,net.arch
Subject: Re: RISC
Message-ID: <262@tellab3.UUCP>
Date: Fri, 31-May-85 11:24:07 EDT
Article-I.D.: tellab3.262
Posted: Fri May 31 11:24:07 1985
Date-Received: Sat, 1-Jun-85 02:31:20 EDT
References: <639@vax2.fluke.UUCP> <2743@nsc.UUCP> <576@terak.UUCP>
Reply-To: thoth@tellab3.UUCP (Marcus Hall)
Organization: Tellabs, Inc., Lisle, IL
Lines: 16
Xref: watmath net.micro.68k:843 net.arch:1288
Summary: 

>RISC is an interesting concept, but I have a major reservation.  Perhaps
>someone can explain to me how on earth you're going to feed instructions
>to a RISC machine fast enough?

One way to help with this problem is to use fairly wide memory accesses
(at least for instruction fetches).  Thus, in one memory cycle, many
instructions may be fetched simultaniously.  Of course this is done for
non-RISC machines as well, but a non-RISC machine will become
execution-bound sooner.

Also, since the RISC instruction set is simpler, the op-codes require fewer
bits, so a memory fetch will get more RISC instructions in one cycle
than it would non-RISC instructions.

marcus hall
..!ihnp4!tellab1!tellab2!thoth