Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.2 9/18/84; site peora.UUCP
Path: utzoo!watmath!clyde!bonnie!akgua!whuxlm!whuxl!houxm!vax135!petsd!peora!joel
From: joel@peora.UUCP (Joel Upchurch)
Newsgroups: net.micro.68k,net.arch
Subject: Re: RISC
Message-ID: <1002@peora.UUCP>
Date: Fri, 31-May-85 13:06:39 EDT
Article-I.D.: peora.1002
Posted: Fri May 31 13:06:39 1985
Date-Received: Sun, 2-Jun-85 00:24:24 EDT
References: <639@vax2.fluke.UUCP> <2743@nsc.UUCP> <576@terak.UUCP>
Organization: Perkin-Elmer SDC, Orlando, Fl.
Lines: 15
Xref: watmath net.micro.68k:846 net.arch:1290


        I think your argument ignores  the  fact  that  with  a  given
        fabrication technology that there is only so much function you
        put on a given chip.  If you chose to  have  a  large  control
        store  ROM  for  a  complex instruction set then you must make
        sacrifices in other parts of the  chip.  This  may  mean  less
        registers,  or  less  cache,  or a slower ALU, or other trade-
        offs.

        RISC argues that  this  is  not  a  good  trade,  that  it  is
        difficult  to  write  compilers to use complicated instruction
        sets and that these high level operations are not  necessarily
        any  faster  than a series of low level operations.  Also with
        simple instruction sets you have the option of hardwireing  it
        for additional performance.