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From: freeman@spar.UUCP (Jay Freeman)
Newsgroups: net.arch
Subject: I like segmented architectures
Message-ID: <276@spar.UUCP>
Date: Fri, 31-May-85 13:59:21 EDT
Article-I.D.: spar.276
Posted: Fri May 31 13:59:21 1985
Date-Received: Sun, 2-Jun-85 07:06:48 EDT
Reply-To: freeman@max.UUCP (Jay Freeman)
Organization: Schlumberger Palo Alto Research, CA
Lines: 46

References:

[ libation to line-eater ]

The fuss about 64K segments looks like effort wasted beating a
dead horse:  I haven't heard anyone defending 64K segments
as the right size, or opposing them as too big.  Now that we all
agree, I suggest that there are some virtues of segmentation that
have been overlooked, having to do with memory-management and
task-switching.

In the recent Intel hardware, the full description of a segment
consists of a base address, a length, and some stuff about access
rights.  (Max length is still 64K in the 286, but is rumored to be
4G (32-bit segment registers) on the 386.)  Every memory reference
explicity involves a segment, and whenever a segment is loaded into
a segment register, all this information about it is brought onto
the chip.  However, the information is not accessible to the user
-- its on-chip location is protected.

Thus, in parallel with the address calculations for memory references,
the CPU itself can decide whether the reference is legal, without
having to consult any additional hardware or software.  Given the
expense in silicon real estate to do this in parallel, there is no
speed penalty at all.

Only when the contents of a segment register are changed, does an
additional decision about memory protection need to be made:  The
operating system will likely maintain for each job, a list of segments
(all information -- base, length, access ...) that it is allowed
to load.  The operating system need not concern itself with the
details of what the jobs do with their segments -- the on-chip
operations should ensure that proper restrictions are observed.

The part of task-switching that involves memory management then
boils down to exchanging my list of allowed segments for yours.

The recent Intel stuff also has a layer of indirection built into the
segment basing, so as to support virtual memory easily.

I suggest that these features are sufficiently useful, that the
allocation of silicon and the provision of software to support them, 
should not be dismissed as a trivial and obvious mistake:  True
fans of the 68XXX and 32XXX would clearly not wish to win merely by 
exploiting public ignorance of their adversary's strengths.

What's more, I love goto's and I hate comments!!! :-)
-- 
Jay Reynolds Freeman (Schlumberger Palo Alto Research)(canonical disclaimer)