Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version nyu B notes v1.5 12/10/84; site acf4.UUCP Path: utzoo!linus!philabs!cmcl2!acf4!tsc2597 From: tsc2597@acf4.UUCP (Sam Chin) Newsgroups: net.arch Subject: Differences between 8088 and 80286 ? Message-ID: <290008@acf4.UUCP> Date: Sat, 1-Jun-85 20:37:00 EDT Article-I.D.: acf4.290008 Posted: Sat Jun 1 20:37:00 1985 Date-Received: Sun, 2-Jun-85 20:19:15 EDT Organization: New York University Lines: 22 <> Recently there has been some discussion on net.micro about a 8 Mhz 8088 being faster than a 6 Mhz 80286. In particular, it was a comparison of benchmarks written in diffrent dialects of BASIC on a Zenith Z-100 and an IBM AT. Gubbins@radc-tops claimed that the Z-100 with an 8 Mhz 8088 is faster than an AT because of the one wait state penalty on memory reference instructions on the AT. I don't want to drag that discussion to this newsgroup but not being familiar with 80286 internals I was wondering if anyone knows precisely what hardware in the Intel 286 makes its instructions take fewer cycles than on the 8088. Is it replacement of microcode with more hardware? Pipelining? Larger Cache? Which instruction types are the 80286 best at and which are they worst at? (in comparision to the 8088 if possible) What documents from Intel or Independent parties are available which describe in detail the design of the 80286. How much CAD was used in the design of the 80286 and how many man-years did it take? Sam Chin USENET: allegra!cmcl2!acf4!tsc2597 ARPA : tsc2597.acf4@nyu