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From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: net.arch
Subject: Re: I like segmented architectures
Message-ID: <5653@utzoo.UUCP>
Date: Mon, 3-Jun-85 12:04:49 EDT
Article-I.D.: utzoo.5653
Posted: Mon Jun  3 12:04:49 1985
Date-Received: Mon, 3-Jun-85 12:04:49 EDT
References: <276@spar.UUCP>
Organization: U of Toronto Zoology
Lines: 87

> I suggest that these features are sufficiently useful, that the
> allocation of silicon and the provision of software to support them, 
> should not be dismissed as a trivial and obvious mistake:  True
> fans of the 68XXX and 32XXX would clearly not wish to win merely by 
> exploiting public ignorance of their adversary's strengths.

Unfortunately for Intel, these are also strengths of the 68XXX and the
32XXX; it's just a little less conspicuous, because it's more transparent.
Herewith an explanation, in the context of the 32XXX (because I'm not too
familiar with the 1000 different 68XXX MMUs).

> ...  Every memory reference
> explicity involves a segment

32XXX:  every memory reference explicitly involves a page number, although
it's not quite so obvious since you don't have to care about your memory
being split up into pages.  (Well, not much.)

> and whenever a segment is loaded into
> a segment register, all this information about it is brought onto
> the chip.  However, the information is not accessible to the user
> -- its on-chip location is protected.

32XXX:  whenever a page is being accessed frequently, all the page-table
information about it is brought into the MMU's cache.  This cache is not
accessible to the user.

> Thus, in parallel with the address calculations for memory references,
> the CPU itself can decide whether the reference is legal, without
> having to consult any additional hardware or software.  Given the
> expense in silicon real estate to do this in parallel, there is no
> speed penalty at all.

32XXX:  thus, in parallel with the address calculations for the memory
reference, the MMU can decide whether the reference is legal.  Whether
it consults anything else is nearly irrelevant; chip size is the only
reason why the 32XXX MMU is not part of the CPU chip.  National decided
that good memory management warranted sufficient silicon real estate
that putting it on the CPU chip wasn't practical for the first version.
The 32XXX does slow down when you turn on the MMU, but this translation
overhead is *always* present in the Intel cpus (although Intel has done
a better job of minimizing it, assisted by the on-chip location of their
MMU).  The only speed penalty on the 32XXX that is specifically the
result of the MMU chip being separate (as opposed to being the result of
separate decisions on bus management etc.) is the small overhead involved
in bringing signals on and off chips.

> Only when the contents of a segment register are changed, does an
> additional decision about memory protection need to be made:

32XXX:  Only when the program's reference patterns change does an additional
decision about memory protection (specifically, loading of page-table entries
that are more useful given the new pattern) need to be made.

> The
> operating system will likely maintain for each job, a list of segments
> (all information -- base, length, access ...) that it is allowed
> to load.  The operating system need not concern itself with the
> details of what the jobs do with their segments -- the on-chip
> operations should ensure that proper restrictions are observed.

32XXX:  The page table constitutes the per-job list of all pages that
the job is allowed to access.  The operating system is not involved in
the details of what the jobs do with their pages -- the MMU hardware
ensures that the proper restrictions are observed.

> The part of task-switching that involves memory management then
> boils down to exchanging my list of allowed segments for yours.

32XXX:  The part of task-switching that involves memory management then
boils down to changing one register, the master page-table pointer in
the MMU, which is essentially the list of allowed pages.

> The recent Intel stuff also has a layer of indirection built into the
> segment basing, so as to support virtual memory easily.

32XXX:  the layer of indirection has, of course, been there all along.
The cache on the 32XXX MMU is managed automatically by the hardware,
rather than requiring the programmer (or his compiler) to do the job
itself by explicitly loading segment registers.

> What's more, I love goto's and I hate comments!!! :-)

Spoken like a true 8086 programmer!!! :-)
-- 
				Henry Spencer @ U of Toronto Zoology
				{allegra,ihnp4,linus,decvax}!utzoo!henry