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From: tsc2597@acf4.UUCP (Sam Chin)
Newsgroups: net.micro
Subject: AT vs Z-100 - a myth
Message-ID: <1040024@acf4.UUCP>
Date: Tue, 28-May-85 11:55:00 EDT
Article-I.D.: acf4.1040024
Posted: Tue May 28 11:55:00 1985
Date-Received: Thu, 30-May-85 06:56:17 EDT
Organization: New York University
Lines: 45

<>

To put to rest the myth that the Z-100 can ever be faster than the IBM AT.
I ran the benchmark as suggested by the author of the original note.  I used
both BASICA as supplied by IBM and generic MSBASIC which you can buy from
Microsoft for generic MS-DOS machines (it has no graphics or
communications).  The benchmark was run on an IBM AT with 256K, 1 1.2 Mb
floppy and 1 360K floppy.  It was a normal AT with the 6 Mhz clock as
opposed to the owner enhanced AT with a 8-9 Mhz clock.

        IBM BASICA 3.0   ---------> 71 seconds
        Microsoft MSBASIC --------> 36 seconds

I will also recall my previous benchmark using a 8 Mhz 8086 which came in at
41 seconds. It is very possible that IBM purposely slowed the BASICA 
interpreter to make it compatible with the PC. A few more points:

(1) If the Z-100 is pushed to 8 Mhz using a 8088-2, it will still suffer
from the 1 wait state penalty if you still use 150ns rams. Also most of the
Intel support chips such as the 8253, 8250 and 8251 are rated at 300ns
causing 2 wait states on an i/o cycle.

(2) The 8088 has 8 bit address lines which will always make it slower than
the 8086 or 80286 on memory reference instructions. The 8086 also has an
instruction queue of 6 instructions as opposed to the 8088 which has only 4.
I don't know if the 80286 has any form of cache but judging from its
performance, it probably has a larger cache than the 8086.

(3) You cannot compare the Mhz between the 8088/8086 to the 80286 because
its instructions take fewer cycles. An aquaintance who builds S-100 CPU
boards claims that a 6 Mhz 80286 is equivalent to a 13-14 Mhz 8086.

(4) A lot of manufacturers who are claiming that their new AT compatibles
are 30% faster than the AT because they eliminated the 1 memory wait state
may be dead wrong. Although my 8 Mhz 8086 benchmark was done on 100ns static
ram, I have in the past tried to rate my static ram board against my dynamic
ram board with 150ns dynamic rams. I did a test to eliminate the wait state
by interleaving two boards so that the odd and even addresses were on
different boards thus eliminating any wait states. The improvement was
a measly 5%.


Sam Chin
tsc2597.acf4@nyu.ARPA
allegra!cmcl2!acf4!tsc2597