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From: jchapman@watcgl.UUCP (john chapman)
Newsgroups: net.micro
Subject: Re: AT vs Z-100 - a myth
Message-ID: <1931@watcgl.UUCP>
Date: Thu, 30-May-85 09:14:13 EDT
Article-I.D.: watcgl.1931
Posted: Thu May 30 09:14:13 1985
Date-Received: Fri, 31-May-85 02:17:54 EDT
References: <1040024@acf4.UUCP>
Organization: U of Waterloo, Ontario
Lines: 59

> Sam Chin writes:  <>
> 
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> 
> I will also recall my previous benchmark using a 8 Mhz 8086 which came in at
> 41 seconds. It is very possible that IBM purposely slowed the BASICA 
> interpreter to make it compatible with the PC. A few more points:

  How does slowing something down make it compatible? I can see that
  a graphics program requiring user interaction might in some sense
  be "incompatible" on a faster machine (processor speedup is generally
  seen as a benefit in highly interactive applications though).  In
  addition I think it would be extremely difficult to make a compiler
  generate code which would overall be slowed down by a certain factor.
> 
> (1) If the Z-100 is pushed to 8 Mhz using a 8088-2, it will still suffer
> from the 1 wait state penalty if you still use 150ns rams. Also most of the
> Intel support chips such as the 8253, 8250 and 8251 are rated at 300ns
> causing 2 wait states on an i/o cycle.

  Actually, from what I know, a 150ns dram ought to be able to keep
  up with an 8mhz 8086/8088 (just) with no wait states.  It's whatever
  is used as the dram controlle that introduces the wait states.  As
  an example I have seen an 8203 based board which runs with no wait
  states with a 5mhz 8086/8088 but requires 2-3 when used with an 8mhz
   8086/8088.  The extra wait states are all directly attributable to
  to the peculiar interaction between the 8203 and 8086 (after a certain
  speed the dram won't know if it can service a request by the time
  the 86 needs to know if there will be wait states (in T2) so a
  different signal from the 8203 is used which always puts in the wait
  states.
> 
> (2) The 8088 has 8 bit address lines which will always make it slower than
                         ^^^^^^^ data lines, the address bus is still
     full width I believe.

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> (4) A lot of manufacturers who are claiming that their new AT compatibles
> are 30% faster than the AT because they eliminated the 1 memory wait state
> may be dead wrong. Although my 8 Mhz 8086 benchmark was done on 100ns static
> ram, I have in the past tried to rate my static ram board against my dynamic
> ram board with 150ns dynamic rams. I did a test to eliminate the wait state
> by interleaving two boards so that the odd and even addresses were on
> different boards thus eliminating any wait states. The improvement was
> a measly 5%.
  In some situations I have experienced a 20% difference between the
  static and dynamic ram execution profiles.  It depends heavily on
  the access pattern of the program being executed.> 
> 
> Sam Chin
> tsc2597.acf4@nyu.ARPA
> allegra!cmcl2!acf4!tsc2597
 
 John Chapman
...!watmath!watcgl!jchapman