Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2(pesnta.1.2) 9/5/84; site idsvax.UUCP Path: utzoo!utcs!lsuc!pesnta!idsvax!steiny From: steiny@idsvax.UUCP (Don Steiny) Newsgroups: net.arch,net.lang.c,net.micro,net.micro.pc,net.micro.68k Subject: Re: Re: Re: Need 286 "C" benchmark Message-ID: <146@idsvax.UUCP> Date: Wed, 29-May-85 22:19:10 EDT Article-I.D.: idsvax.146 Posted: Wed May 29 22:19:10 1985 Date-Received: Thu, 30-May-85 09:09:09 EDT References: <426@oakhill.UUCP> <8745@microsoft.UUCP> <583@intelca.UUCP>, <433@oakhill.UUCP> <181@anwar.UUCP> Organization: Personetics, Inc. - Santa Clara Lines: 42 Xref: utcs net.arch:1249 net.lang.c:5218 net.micro:10214 net.micro.pc:4022 net.micro.68k:821 ** Saying that it is unfair to compare the 286 with other chips because there is no huge model compiler is begging the question. Why are there no huge model compilers for the 286 even though many people have been working on it for years? Simple, the 286 is a nightmare for compiler writers. There are no truely general purpose registers in Intel chips. The memory management scheme requires the load a segement discriptor table to get the information about the segments so that the program can get the data from the segment. Note that after the program has the information from the segment discriptor table, it still had to compute the offset in the normal Intel fashion. Though the segmented Intel chips have traditionally been difficult to write compilers for, the 286 is even worse. I was working on some the initial design of the compiler for the AT&T sanctioned port to the 286 as a consultant to DRI. We were having a meeting to discuss the global portions of the the compiler, symbol table, object format, and so on. We were going over the 286 to make sure we all understood it. After a few hours we all were incredulous. Why? We asked. What would motivate such insanity? We figured that it must have some properities that are especially appealing to engineers. We were all software, so we did not appreciate it. I have been using a huge model compiler on a 16032 for several months. It is Tolerant System's 4.2 port to the 16032. It has System V shared memory in addition to the normal 4.2 IPC. There is no problem at all in declaring shared memory segments of 4MB. This is not new, National Semiconductor Genix had huge model many years ago. There are many huge model compilers for the 68k chips. Blame it on Microsoft! :-) Intel is not inherently evil or anything. They have been trying to maintain compatability with their older chips. I have heard rumors that the 386 will have linear address space. Now if they would just give compiler writers a few extra registers to evaluate expressions and computer memory locations . . .