Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/13/84; site intelca.UUCP Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!ihnp4!pesnta!amd!intelca!clif From: clif@intelca.UUCP (Clif Purkiser) Newsgroups: net.micro.68k Subject: Re: Re: 68020 benchmarks?? (disbelieve Intel) Message-ID: <594@intelca.UUCP> Date: Thu, 30-May-85 12:53:35 EDT Article-I.D.: intelca.594 Posted: Thu May 30 12:53:35 1985 Date-Received: Fri, 31-May-85 06:25:43 EDT References: <155@soph.UUCP> <> <157@soph.UUCP> Organization: Intel, Santa Clara, Ca. Lines: 83 > > In article <> phil@amdcad.UUCP (Phil Ngai) writes: > > > > > Gosh, how could a 6 MHz 80286 do as good as a 12 MHz 68010? > > Ummm ... what are you talking about? There is *no such part* as > a 12 MHz 68010. Let's not spread any misinformation here ... > you are drawing some flakey conclusions from those numbers I put > out. > If there is no 12 MHZ 68010, why does Mot claim that a 16.6MHz 68020 is 2.5x performance of a 12 Mhz 68010? > > > > > The 80286 does *not* need faster memory devices than the 68000. What the > > 80286 does do is use the (same cost) memory devices more efficiently than > > the 68000. It's called pipelining and is a well known technique among > > computer professionals. > > Gee ... I must have hit a nerve somehow, to make a nettie resort > to title-dropping. Only, I thought "computer professional" was > a term used only by "MIS Week". > > Actually, the reason the 80286 chews up memory bandwidth is that it > uses a 250 ns. bus cycle (at 8 MHz) vs. a 400 ns. bus cycle for a 10 MHz > 68010. Since you don't have much time to decode the address, you either > use 120 ns. DRAM ($$$$) or add a wait state and slow it down to a 375 ns. > memory cycle. > > Pipelining has nothing to do with it; though it *does* spend a lot of cycles > filling the pipeline, this has nothing to do with the memory speed needed. > -- > Dave Brownell > EnMasse Computer Corporation > enmasse!dave@Harvard.ARPA > {genrad,harvard}!enmasse!dave Actually, the 80286 has two types of pipelining: The internal pipelining which cause the CPU to execute instruction faster on the 286 then the 68010. (e.g ADD AX, #val is only 2 clocks on a 286, compared to 8 clocks for ADD #val, (4 Clocks for the operation and 4 more clocks for the effective address calculation) on a 68010). The other type of pipelining on the 286 is address pipelining. Address pipelining puts the address out 1/2 clock before the start of the next bus cycle. This gives an 8Mhz 286 ~300 nsec of memory access time, when used with an interleaved DRAM design. The 68010 uses 4 clock bus which on the surface implies that you have 400 nsec access time. However, a closer look at the 68010 timimg diagram shows that that the address isn't valid until 70nsec after the start of a bus cycle thus reducing the memory access time to ~330 nsec. So despite, the 286 having a two clock bus (which speeds up instruction execution) compared to a four clock bus for the 68010 the parts have similiar memory access times. Because, the 286 puts out the address 1/2 clock early and the 68010 puts out the address over 1/2 clock late. Before I recieve tons of flames, I'll concede three points: 1. An interleaved DRAM design is more complicated than a non interleaved design 2. I have not discussed several other timings needed to accurately calculate memory access times, because the timing paramaters are similiar (+/- 2ns) between the 68010 @10Mhz and the 286 @8Mhz. 3. Memory access time is not the same as the speed DRAMs you need. Of course, I also have not talked about the fun the hardware engineers have designing a MMU that runs a zero wait states with the 68010. -- Clif Purkiser, Intel, Santa Clara, Ca. HIGH PERFORMANCE MICROPROCESSORS {pur-ee,hplabs,amd,scgvaxd,dual,idi,omsvax}!intelca!clif {standard disclaimer about how these views are mine and may not reflect the views of Intel, my boss , or USNET goes here. }