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Path: utzoo!watmath!clyde!burl!ulysses!ucbvax!info-vax
From: info-vax@ucbvax.ARPA
Newsgroups: fa.info-vax
Subject: uVAX busses (more rumors)
Message-ID: <7851@ucbvax.ARPA>
Date: Wed, 5-Jun-85 19:48:52 EDT
Article-I.D.: ucbvax.7851
Posted: Wed Jun  5 19:48:52 1985
Date-Received: Thu, 6-Jun-85 06:36:34 EDT
Sender: daemon@ucbvax.ARPA
Organization: University of California at Berkeley
Lines: 17

From: "Brand Hal"@LLL-MFE.ARPA


   Sorry, but I just have to throw in the rumors going around here:

1) The uVAX II is single chip with optional FPA chip implementing uVAX
    architecture (not full VAX) using the Q-Bus for I/O and the C/D (seedy)
    interconnect for a private memory interconnect (bus sorta).
2) The uVAX III is the same chip(s), just on the BI.   Rumor is that silicon
    already exists and functions for the BI interface chip.
3) The uVAX IV will be a new chip set implementing the full VAX architecture
    (includeing compatability mode - uuuugh), also utilizing the BI for
    I/O atleast, and who knows about memory.   Supposedly, this chip set will
    outperform the uVAX II chip(s).

Remember, all this is rumors (except maybe 1 which can now be confirmed by
examining real hardware!!!