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Path: utzoo!watmath!clyde!bonnie!akgua!whuxlm!whuxl!whuts!brt
From: brt@whuts.UUCP (B Reytblat)
Newsgroups: net.arch
Subject: Re: The little assembler that lies...
Message-ID: <128@whuts.UUCP>
Date: Mon, 3-Jun-85 11:36:56 EDT
Article-I.D.: whuts.128
Posted: Mon Jun  3 11:36:56 1985
Date-Received: Wed, 5-Jun-85 01:07:17 EDT
References: <893@sdcsvax.UUCP> <2465@wateng.UUCP>
Organization: AT&T Bell Laboratories
Lines: 81

> >     The  BELLMAC-32  processor  (a.k.a.  WE-3200x)  has  an
> >instruction,  called  RESTORE which restores a set of regis-
> >ters from the stack....... However, the as assembler
> >insists on mapping  this  single  instruction  to  up  to  7
> >instructions.......???
> 
> Another possibility is that the RESTORE instruction
> might not operate properly for all CPU's.  Maybe the assembler is working
> around a buggy mask set?
> 			Kevin
> -- 
> Kevin Szabo  watmath!wateng!ksbszabo (U of Waterloo VLSI Group, Waterloo Ont.)

*** REPLACE THIS MESSAGE WITH YOUR LINE ***

  I have not yet had an opportunity to talk to Darryl Long (the poster of the original 
article). I would, however, like to respond to Kevin's suggestion:

	It is most emphatically NOT the case ! The RESTORE instruction does operate 
properly  on all WE 3200x* Microprocessors I have ever tried (several 3B2's, one 3B5 and
a bunch of WE 320EB's and WE 320AP's).

Here's a little exercise I have just performed (I'm running on an Amdhal w/ Sys 5 and 
 the following version of WE3200x Microprocessor Tools:
		m32: command -Release 5.0.1.2 4/25/82 for (3B2) )

Source:

	main() {
		int a;
		a ++;
	}

I do "m32cc -S try1.c" and get back try1.s:


	.file	"try1.c"
	.data
	.text
	.align	4
	.def	main;	.val	main;	.scl	2;	.type	044;	.endef
	.globl	main
main:
	save	&.R1
	addw2	&.F1,%sp
	addw2	&1,0(%fp)
.L12:
	.set	.R1,0
	ret	&.R1
	.set	.F1,4
	.def	main;	.val	.;	.scl	-1;	.endef
	.data
		****  m32 DISASSEMBLER  ****

I then do "m32cc -c try1.s; m32dis try1.o" and get back :

disassembly for try1.o

section	.text
main()
	   0:  10 49                         SAVE    %fp
	   2:  9c 4f 04 00 00 00 4c          ADDW2   &0x4,%sp
	   9:  90 59                         INCW    0(%fp)
	   b:  70                            NOP     
	   c:  18 49                         RESTORE %fp
	   e:  08                            RET     
	   f:  70                            NOP     


As you can see, the IS25 instruction "ret	&.R1" got translated into
two WE3200x Microprocessor instructions: "RESTORE %fp" and "RET". NOT
a bunch of POP's !!!
I don't understand how Darryl is running into his problem, but would be
glad to talk to him, or anyone else about it.
My phone number is (201)-981-2044.

	Hope this helps,
			Ben Reytblat. AT&T Bell Laboratories.


* WE is a registered trademark of AT&T Technologies