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From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: net.micro.68k,net.arch
Subject: Re: RISC
Message-ID: <5673@utzoo.UUCP>
Date: Thu, 6-Jun-85 12:09:23 EDT
Article-I.D.: utzoo.5673
Posted: Thu Jun  6 12:09:23 1985
Date-Received: Thu, 6-Jun-85 12:09:23 EDT
References: <639@vax2.fluke.UUCP> <2743@nsc.UUCP> <576@terak.UUCP> <611@lll-crg.ARPA>, <591@terak.UUCP>
Organization: U of Toronto Zoology
Lines: 19

> I thought this too, until I looked into some RISC machines.  They use
> 32-bit instruction words, twice as wide as the equivalent instructions
> in, say, the 680xx and 320xx cpus.

Yes and no.  The Berkeley RISC project adopted 32-bit instructions for
simplicity in initial work, not because they thought it was right for
the final design.  If you look, you'll find at least one paper from them
discussing a support chip which is (a) an instruction cache, and (b) an
instruction-encoding expander.  The latter function makes a large
difference to instruction density without introducing any extra delays.

Also, don't be too sure that the 68* and 32* chips use 16-bit instructions
a lot.  Remember that things like offsets take extra bytes, and those get
used *a lot* on those machines -- virtually every memory reference needs
one.  On the pdp11, a 16-bit machine if there ever was one, the average
instruction length was in fact about 32 bits.
-- 
				Henry Spencer @ U of Toronto Zoology
				{allegra,ihnp4,linus,decvax}!utzoo!henry