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Path: utzoo!watmath!wateng!ksbszabo
From: ksbszabo@wateng.UUCP (Kevin Szabo)
Newsgroups: net.lsi,net.arch
Subject: Re: Standard cells vs gate arrays in cost
Message-ID: <2505@wateng.UUCP>
Date: Tue, 11-Jun-85 22:52:29 EDT
Article-I.D.: wateng.2505
Posted: Tue Jun 11 22:52:29 1985
Date-Received: Wed, 12-Jun-85 02:14:45 EDT
References: <291@ihlpm.UUCP>
Reply-To: ksbszabo@wateng.UUCP (Kevin Szabo)
Distribution: net
Organization: VLSI Group, U of Waterloo
Lines: 26
Xref: watmath net.lsi:112 net.arch:1360
Summary: 

In article <291@ihlpm.UUCP> crowley@ihlpm.UUCP (Opus) writes:
>                    It stated that gate arrays are cheaper to
>develop than standard cells. Could someone explain why this is?
>I always thought that standard cells would be cheaper because
>of being able to use function blocks in the design of it.
>Gate arrays would be more expensive because of using gate level
>blocks to design it.

Short but sweet...gate arrays are pre-arranged transistors
interconnected as gates.  They are predesigned and prefabricated just
up to the point of adding the metalization.  The designer determines
his wiring list and that is mapped onto the metallization layer.  In
standard cell design the standard cells are functional blocks (ram,
nand alu's etc) that are chosen by the designer and interconnected.
Note that this chip cannot be prefabricated, it must have a full
complement of masks made for each design.  The photolithography cost
and the inability to prefabricate the chip are the major costs.  Gate
array's are harder to use since you have to "map your problem to the
solution" but they have the fastest turn around time of all the VLSI
design techniques.

I can elaborate a little more if you want.

			Kevin
-- 
Kevin Szabo' watmath!wateng!ksbszabo (U of W VLSI Group, Waterloo, Ont, Canada)