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From: kds@intelca.UUCP (Ken Shoemaker)
Newsgroups: net.micro.68k,net.micro.pc,net.arch
Subject: Re: Re: x86/68x buses ; two-level microcode
Message-ID: <611@intelca.UUCP>
Date: Tue, 11-Jun-85 19:08:02 EDT
Article-I.D.: intelca.611
Posted: Tue Jun 11 19:08:02 1985
Date-Received: Wed, 12-Jun-85 10:26:18 EDT
References: <344@osu-eddie.UUCP> <600@intelca.UUCP> <2275@sun.uucp>
Organization: Intel, Santa Clara, Ca.
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Xref: utcs net.micro.68k:899 net.micro.pc:4191 net.arch:1355

> Well, I was just reading a trade rag that quoted Intel and AMD as
> having REDUCED the price of the 80186 by 50% to $15-20 for 25K.  We got
> quotes of about $10 for 10MHz 68000's in quantity last month.
> All those pins are really driving up the price...

This is comparing apples and oranges, for two reasons: the first is
date of introduction of the two products, and the second is that price
has little to do with cost.  But think about it, how can a 64 pin
package ever be cheaper than a 48 pin package?  It takes more material,
for sure, but in addition to that, it requires more board space and
a tester for the device would require additional lines for the extra
pins (which usually means a more expensive tester).
> 
> One advantage of the 680x0 approach is that you don't have to surround
> your CPU with glue to latch the addresses.  You can just wire address
> pins straight to where they're going and they stay good for the entire
> cycle.  I agree that there might be potential for speed improvement
> here, so just think -- in a few years when the 68020 seems like a slow
> machine, they'll have a few more tricks they can pull.

Sure, you are going to drive 2Mbytes of static RAMs (or ROMs?) directly
off the pins of the processor?  Surely you need an address buffer in there
somewhere, or are those not considered "glue"?

> 
> Here's some detail on memory cycle and address-to-data times for 68Ks:
> 
> 	Part		ClkCyc	Clk/Mem	MemCyc	Addr->data
> 	68000L4	 	250ns	4      1000ns	630ns
> 	68000L10	100ns	4	400ns	230ns
> 	68010L10	100ns	4	400ns	235ns
> 	68000L12	 80ns	4	320ns	175ns
> 	68010L12	 80ns	4	320ns	175ns
> 	68020R12	 80ns	3	240ns	150ns
> 	68020R16	 60ns	3	180ns	115ns
> 
> Note that the 68000L4 was the first to be announced and the 68020R16
> is the last to be announced.  There's a factor of 5 between the two
> just in bus cycle times.  [I don't think you can buy 68000L4 anymore;
> just about any die that runs at 4MHz also runs at 8 or more...]

Is a factor of 5 good news?  Just think, your whole memory system has to
be sped up by 5 times!  Memory designers may be good, but they aren't THAT
good!  If Mot had gone with pipelined address/data on the 68020R16,
I'd guess that their memory access times (addr->data) would go from
115ns to 170ns.  However, they may use pipelining internally to access
their cache, so they can never allow this extra margin for system 
designers (does anyone know if this is true?).
-- 
It looks so easy, but looks sometimes deceive...

Ken Shoemaker, 386 Design Team, Intel, Santa Clara, Ca.
{pur-ee,hplabs,amd,scgvaxd,dual,qantel}!intelca!kds
	
---the above views are personal.  They may not represent those of Intel.