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From: doug@terak.UUCP (Doug Pardee)
Newsgroups: net.micro.68k,net.arch
Subject: Re: RISC
Message-ID: <604@terak.UUCP>
Date: Tue, 11-Jun-85 11:39:42 EDT
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Posted: Tue Jun 11 11:39:42 1985
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Once again, I find that I didn't do a good job of explaining myself.
Let me try again...

In the following comment, notice the word "equivalent":

me> I thought this too, until I looked into some RISC machines.  They use
me> 32-bit instruction words, twice as wide as the equivalent instructions
me> in, say, the 680xx and 320xx cpus.

> Also, don't be too sure that the 68* and 32* chips use 16-bit instructions
> a lot.  Remember that things like offsets take extra bytes, and those get
> used *a lot* on those machines -- virtually every memory reference needs
> one.

My point was supposed to be that you could take a 680xx/320xx and limit
yourself to the RISC instruction set (the "equivalent" instructions) and
have 16-bit instructions instead of RISC's 32-bit instructions.

Presumably, the reason that the longer instructions, with their offsets
etc., are used so much is because those instructions are more effective
than the RISC instructions for the task at hand (this sounds like
another discussion that I'm involved in :-)

> instruction-encoding expander.  The latter function makes a large
> difference to instruction density without introducing any extra delays.

In a microcoded cpu, the opcode is decoded and causes a sequence of
very simple micro-instructions to be executed.

In the proposed system, the opcode is decoded and causes a sequence of
very simple RISC instructions to be executed.

What's the difference?  Where does the much-vaunted performance gain
come from?
-- 
Doug Pardee -- Terak Corp. -- !{ihnp4,seismo,decvax}!noao!terak!doug
               ^^^^^--- soon to be CalComp