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From: gnu@sun.uucp (John Gilmore)
Newsgroups: net.arch
Subject: Orthogonal addressing doesn't help multis.
Message-ID: <2305@sun.uucp>
Date: Sat, 15-Jun-85 04:49:36 EDT
Article-I.D.: sun.2305
Posted: Sat Jun 15 04:49:36 1985
Date-Received: Mon, 17-Jun-85 03:40:17 EDT
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Organization: Sun Microsystems, Inc.
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> And furthermore, the orthogonal sequence is normally atomic...
> 	Mark Wittenberg

This is untrue on machines I know of.  Typical memory-to-memory
instructions do NOT lock out other memory cycles in between; this
requires a specific "test-and-set" or "compare-and-swap" instruction.
This is because often other cycles can be interspersed between the
reads of the operands and the write of the result -- e.g. an
instruction prefetch, or another data fetch.  I have not checked
this in National data books (I'm at home) but I'd be surprised if
they lock the bus for the duration.

Assuming the above is true, it means that even a single instruction
e.g. add  _a,_b  cannot assume that 'b' will not be accessed by another
processor (or dma I/O device) in mid-instruction.  This is equivalent
to the load, add, store case.  On some machines the window where you
can get hurt is smaller for the 1-instruction case, but it still exists.

I once proposed adding a mode to the 68000 that would cause bus locking
for memory read/write instructions (eg, add 1 to counter), but they never
implemented it -- probably for good reason.  The 68020 includes compare
and swap, which allows arbitrary multi-instruction sequences of operations
and verifies that nobody has snuck in in the middle, with very minimal
penalty (an extra read) in the common case.  The IBM 370 principles
of operation manual used to have excellent examples of how to use it.
The 68020 manual does too, I believe.