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From: mfe@leadsv.UUCP (Mark Ellson)
Newsgroups: net.lsi,net.arch
Subject: Re: Standard cells vs gate arrays in cost
Message-ID: <471@leadsv.UUCP>
Date: Wed, 12-Jun-85 10:58:04 EDT
Article-I.D.: leadsv.471
Posted: Wed Jun 12 10:58:04 1985
Date-Received: Thu, 20-Jun-85 07:37:19 EDT
References: <291@ihlpm.UUCP>
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Organization: LMSC-LEADS, Sunnyvale, Ca.
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Xref: watmath net.lsi:113 net.arch:1425
Summary: Gate arrays and standard cells are both designed with macro cells.

In article <291@ihlpm.UUCP>, crowley@ihlpm.UUCP (Opus) writes:
> In the June 1985 issue of VLSI Design magazine there is an article
> titled "PLDs As Semicustom Substitutes". This article discusses the
> cost to develop programmable logic devices (PLDs), gate arrays,
> and standard cells. It stated that gate arrays are cheaper to
> develop than standard cells. Could someone explain why this is?

In designing any semi-custom chip, either gate array or standard cell, you
will typically use a set of functional blocks or macro cells which have been
provided by your foundry.  In a standard cell design, the macro cells have
been compacted to minimize size within the constraint of having a fixed
height but with variable width.  In gate arrays, the macro library may exist
only at the netlist level (a soft macro), or the foundries layout tools may
require that all of the gates in a macro be grouped together with a specific
metallization pattern (a hard macro).  The hard macro will typically give
you better performance for the cell since all of the internal delays are
known, and hopefully minimized.  The advantage of a soft macro is more
flexibility in routing the metallization.

The real savings in designing gate arrays is in the reduced layout times
because all you are concerned with is the final metallization, and reduced
tooling costs because you need substantially fewer masks to produce your
design.  Also, the turn around time for gate array prototypes is generally
about 4 weeks shorter.  In many of the designs which we do here this quicker
turn around is really the deciding factor in favor of gate arrays.

				Mark Ellson
				Lockheed Missiles & Space Co.
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