Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 (Tek) 9/28/84 based on 9/17/84; site mako.UUCP Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxt!houxm!mtuxo!mtunh!mtung!mtunf!ariel!vax135!cornell!uw-beaver!tektronix!orca!mako!jans From: jans@mako.UUCP (Jan Steinman) Newsgroups: net.arch Subject: Re: Orthogonal addressing doesn't help multis. Message-ID: <831@mako.UUCP> Date: Tue, 25-Jun-85 00:26:20 EDT Article-I.D.: mako.831 Posted: Tue Jun 25 00:26:20 1985 Date-Received: Thu, 20-Jun-85 20:35:45 EDT References: <419@oakhill.UUCP> <6415@boring.UUCP> Reply-To: jans@mako.UUCP (Jan Steinman) Organization: Tektronix, Wilsonville OR Lines: 39 Summary: In article <2305@sun.uucp> gnu@sun.uucp (John Gilmore) writes, quotes: >>Mark Wittenberg: >>And furthermore, the orthogonal sequence is normally atomic... > >This is untrue on machines I know of. Typical memory-to-memory instructions >do NOT lock out other memory cycles in between; this requires a specific >"test-and-set" or "compare-and-swap" instruction... I have not checked this >in National data books but I'd be surprised if they lock the bus... It appears Nati has done this properly. Operands which are read and written are of the special access class "rmw", which in itself is nothing special, because it is desirable to allow >... other cycles... [to] be interspersed between the reads of the operands >and the write of the result... and therefore the CPU is not the proper chip to decide to lock the bus. The Nati processors display the fact that a read cycle of a "rwm" cycle is about to begin *one clock before it actually begins*, allowing a user-supplied interlock on multi-processor systems plenty of time to keep other processors out without penalizing uni-processor designs with excessivly long rwm cycles. It would be nice if you could throw a switch in the Nati MMU to do this for you, but I guess they only had so much silicon... Asking designers to handle this is not unusual and is not at all bad. The "interlock" operations on Nati bit instructions simply wag the ILO line, leaving the designer with the task of determining the most efficient manner to utilize this information, while the 68000 goes to the trouble of providing a special, 20 clock memory cycle for a single instruction, TAS, which simply tests and sets the MSB of the operand byte. With the proper hardware looking at the CPU status, it should be easy to insure atomic access during any "rwm" cycle, which is used orthogonally throughout the Nati instruction set. It is interesting to note that all three of the papers presented in the Usenix Conference Multi-Processing session were on Nati processors, although neither machine evidently implemented an atomic "rmw" access class. -- :::::: Jan Steinman Box 1000, MS 61-161 (w)503/685-2843 :::::: :::::: tektronix!tekecs!jans Wilsonville, OR 97070 (h)503/657-7703 ::::::