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From: steve@kontron.UUCP (Steve McIntosh)
Newsgroups: net.arch
Subject: Re: Novix Forth chip seen at Rochester Conference
Message-ID: <255@kontron.UUCP>
Date: Thu, 20-Jun-85 14:06:11 EDT
Article-I.D.: kontron.255
Posted: Thu Jun 20 14:06:11 1985
Date-Received: Fri, 21-Jun-85 07:42:38 EDT
References: <249@tekcbi.UUCP> <89300001@hpisla.UUCP>
Organization: Kontron Electronics, Irvine, CA
Lines: 26

> >...the
> >following must be taken with a killogram of NaCl....
> 
>   So, I think, should the preceding.
>   Unless I am missing something, even an *extremely* complex processor
>   could execute only 8 "Million Forth primitives per second (at a clock
>   rate of 8 MHz)."
> 
> David Wolpert

David - the FORTH chip is really a RISC machine using the Forth 
virtual machine as a model. It can execute more primatives per
second than clocks per second because the 16 bit opcodes (executed
in one clock cycle) can specify several primatives in parallel.
As an example, the forth phrase DUP @ SWAP nn + which is useful
for marching thru a data structure is one opcode on the Forth chip.
 
Much of the reason that this can be done is that the chip accesses
main memory, the data stack and the return stack in parallel. It can
access 48 bits of data on each clock cycle as well as the top two
items of the data stack, which are kept in registers.

It is possible that this chip may show up as the core of a single
user workstation, but its main market is for use as an embedded
control processor. It will be some time before it is seen in
"general purpose" computers, if ever. (more's the pity.)