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From: doug@terak.UUCP (Doug Pardee)
Newsgroups: net.arch
Subject: Re: Orthogonal addressing doesn't help multis.
Message-ID: <613@terak.UUCP>
Date: Tue, 18-Jun-85 14:15:13 EDT
Article-I.D.: terak.613
Posted: Tue Jun 18 14:15:13 1985
Date-Received: Sun, 23-Jun-85 07:33:12 EDT
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Organization: Terak Corporation, Scottsdale, AZ, USA
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> > And furthermore, the orthogonal sequence is normally atomic...
> 
> This is untrue on machines I know of.  Typical memory-to-memory
> instructions do NOT lock out other memory cycles in between; this
> requires a specific "test-and-set" or "compare-and-swap" instruction.
> This is because often other cycles can be interspersed between the
> reads of the operands and the write of the result -- e.g. an
> instruction prefetch, or another data fetch.  I have not checked
> this in National data books (I'm at home) but I'd be surprised if
> they lock the bus for the duration.

The NS320xx provides the special instructions SBITI, CBITI, and IBITI
(Set/Clear/Invert Bit Interlocked) which activate the "ILO*" pin on the
CPU for the duration of the instruction.
-- 
Doug Pardee -- Terak Corp. -- !{ihnp4,seismo,decvax}!noao!terak!doug
               ^^^^^--- soon to be CalComp