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From: crowley@ihlpm.UUCP (Opus)
Newsgroups: net.lsi,net.arch
Subject: Standard cells vs gate arrays in cost
Message-ID: <291@ihlpm.UUCP>
Date: Mon, 10-Jun-85 17:00:31 EDT
Article-I.D.: ihlpm.291
Posted: Mon Jun 10 17:00:31 1985
Date-Received: Tue, 11-Jun-85 05:04:10 EDT
Distribution: net
Organization: AT&T Bell Laboratories
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Xref: watmath net.lsi:111 net.arch:1356

In the June 1985 issue of VLSI Design magazine there is an article
titled "PLDs As Semicustom Substitutes". This article discusses the
cost to develop programmable logic devices (PLDs), gate arrays,
and standard cells. It stated that gate arrays are cheaper to
develop than standard cells. Could someone explain why this is?
I always thought that standard cells would be cheaper because
of being able to use function blocks in the design of it.
Gate arrays would be more expensive because of using gate level
blocks to design it.
					Bob Crowley
					ihlpm!crowley
					Bell Labs - Naperville

	send all flames to /dev/`tty`  (:-))