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From: pdbain@wateng.UUCP (Peter Bain)
Newsgroups: net.mag
Subject: TOC, IEEE Trans. COmputers May 1985
Message-ID: <2541@wateng.UUCP>
Date: Tue, 18-Jun-85 13:08:29 EDT
Article-I.D.: wateng.2541
Posted: Tue Jun 18 13:08:29 1985
Date-Received: Wed, 19-Jun-85 03:18:05 EDT
Distribution: net
Organization: U of Waterloo, Ontario
Lines: 77

%A Howard M. Shao
%A T.K. Truong
%A Leslie J. Deutsch
%A Joseph H. Yuen
%T A VLSI Design of a Pipleline Reed-Solomon Decoder
%J IEEE Trans. on Computers
%I IEEE
%V C-34
%N 5
%D May 1985
%P 393-403
%K systolic array error detecting correcting codes

%A Lionel M. Ni
%A Kai Hwang
%T Vector Reduction Techniques for Arithmetic Pipelines
%J IEEE Trans. on Computers
%I IEEE
%V C-34
%N 5
%D May 1985
%P 404-411
%K interleaving matrix algebra multiple vector processing VLSI
architecture

%A Kyungsook Yoon Lee
%T On the Rearrangeability of 2(log(2) N) -1 Stage Permutation Networks
%J IEEE Trans. on Computers
%I IEEE
%V C-34
%N 5
%D May 1985
%P 412-425
%K control algorithm hardware redundancy multistage interconnection
networks

%A Sunil K. Jain
%A Vishwani D. Agrawal
%T Modeling and test Generation Algorithms for MOS Circuits
%J IEEE Trans. on Computers
%I IEEE
%V C-34
%N 5
%D May 1985
%P 426-433
%K D-algorithm integrated VLSI circuit testing transistor faults

%A Dhiraj K. Pradhan
%T Dynamically Restructurable Fault-Tolerant Processor Network
Architectures
%J IEEE Trans. on Computers
%I IEEE
%V C-34
%N 5
%D May 1985
%P 434-447
%K binary tree distributed system interconnection packet switching
parallel systems processor arrays self-routing

%A Tom Leighton
%A Charles E. Lieserson
%T Wafer Scale Integration of Systolic Arrays
%J IEEE Trans. on Computers
%I IEEE
%V C-34
%N 5
%D May 1985
%P 448-461
%K channel width fault tolerant systems matching travelling salesman
problem VLSI spanning tree meshes wire lengths

-- 
   - peter bain
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