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From: gnu@sun.uucp (John Gilmore)
Newsgroups: net.micro,net.arch
Subject: Re: what really happens during a bus acknowledge?
Message-ID: <2262@sun.uucp>
Date: Sun, 2-Jun-85 20:27:36 EDT
Article-I.D.: sun.2262
Posted: Sun Jun  2 20:27:36 1985
Date-Received: Thu, 6-Jun-85 01:18:32 EDT
References: <650@abnji.UUCP>
Organization: Sun Microsystems, Inc.
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Xref: watmath net.micro:10658 net.arch:1309

In the 68020, when the bus is granted to a DMA device, the CPU
continues to fetch and execute instructions.  If a prefetch misses the
on-chip instruction cache, or a data reference occurs, it will hang;
otherwise, it will continue execution.

The 68000 and 68010 would continue executing instructions like multiply
or shift while the bus was granted, but would hang immediately after
the instruction finished because it had to fetch another.  In general,
any CPU that doesn't have an on-chip cache will have to stop pretty
soon.  Unless the bus is a lot faster than the CPU (they were about
evenly matched in the 68000; I hear the CPU was faster than the bus in
the 8086 and especially in the 8088), the prefetch queue will not be
very full, so even a chip with a deep prefetch will stall pretty soon.
Of course, if you are only stealing one DMA cycle then you might luck
out; but it's more efficient to steal 20 DMA cycles at once than to
steal one 20 times, since you lose a lot in arbitration delays.

Signetics has an interesting part in design called the MAC (Memory
Access Controller) for 680xx family parts.  It's an MMU which manages a
local cache memory.  It lets you map each page of main memory as
"local" or "global" memory to keep the global bus traffic separate.  It
kind of does what you are talking about on a multiprocessor level
rather than on a CPU chip level.